Delay locked loops (DLLs) are used to align data output from circuits, such as memory circuits, to the clock signal of a host. A DLL receives a clock signal from a host and provides a DLL signal to an off chip driver (OCD) to align data output from the circuit to the clock signal of the host. The DLL compensates for differences in timing between the circuit and the host. Off chip drivers typically have a rising edge propagation delay through the off chip driver that is different from the falling edge propagation delay through the off chip driver.
Typically, DLLs account for the rising edge propagation delay through the off chip driver, but do not account for the falling edge propagation delay through the off chip driver. For example, while a logic high data signal that generates a rising edge signal through the off chip driver may be aligned with the rising edge of the clock signal of the host, a logic low data signal that generates a falling edge signal through the off chip driver may not be aligned with the falling edge of the clock signal of the host.